The present invention relates to a thin-film transistor (TFT), and more particularly, to an amorphous silicon TFT wherein an ohmic contact layer and active layer are improved and to a fabricating method thereof.
Thin-film transistors generally include an active layer of amorphous silicon, polysilicon or cadmium-selenium and have been widely employed as the pixel-driving elements of a liquid crystal display device. Particularly, a hydrogenated amorphous silicon (a-Si:H) TFT is advantageous to the production of large-screen displays and facilitates mass production. When employing the a-Si:H layer, the main concerns are enhancing field-effect mobility while maintaining a low off-current characteristic. Here, it should be noted that the high photo-conductivity properties of hydrogenated amorphous silicon generate high levels of leakage current under backlight illumination, and if a high-intensity backlight is adopted, as in the case of projection-type displays, the leakage current becomes a serious problem. Thus, reducing the photo leakage-current of an a-Si:H TFT is an essential task to obtain a high quality TFT-LCD. Though the leakage current can be lowered by reducing the thickness of an undoped a-Si:H layer, unfortunately, this also decreases field-effect mobility.
Recently, however, an n.sup.+ -type microcrystalline silicon (n.sup.+ .mu.c-Si) having a wide energy-band gap has been developed using SiH.sub.2 Cl.sub.2 gas and applied to fabricate an a-Si:H TFT having low leakage current. In contrast to n.sup.+ a-Si:H, n.sup.+ microcrystalline silicon has a relatively low sheet resistance and high conductivity, so that hole current is effectively blocked during an off-operation of the TFT and on-current is increased.
Meanwhile, the structure of the amorphous silicon TFT can be roughly classified into staggered and coplanar types according to the location of a patterned active layer. In the case of the staggered type, a gate electrode and source/drain electrode are separated by an interposed semiconductor layer, differently from the coplanar type in which the electrodes are all formed in the same side of a semiconductor layer. Here, the most widely used amorphous silicon TFT is the inverse-staggered type.
FIG. 1 is a cross-sectional view of a conventional inverse-staggered type amorphous silicon TFT.
As shown in FIG. 1, gate 11 consisting of a metal pattern of chromium or aluminum is formed on insulating substrate 10, and gate insulating layer 12 made of nitride is formed on the whole surface of the resultant. On gate insulating layer 12, the channel of the TFT is formed of a patterned layer of hydrogenated amorphous silicon, as active layer 13, and source/drain 15 is formed on both sides of the active layer. Then, to improve ohmic characteristics, ohmic contact layer 14 doped with a high concentration of n-type impurities is formed between active layer 13 and source/drain electrode 15. Here, the n.sup.+ .mu.c-Si used as ohmic contact layer 14 is formed by depositing H.sub.2 /SiH.sub.4 gas (mixed with a ratio of 10:1) or SiF.sub.4 /H.sub.2 /SiH.sub.4 gas using a plasma-enhanced chemical vapor deposition (PECVD) method.
However, if H.sub.2 /SiH.sub.4 gas is used for depositing the conventional n.sup.+ .mu.c-Si layer, the deposition rate is remarkably decreased and particles are generated, due to the etching effect of hydrogen. On the other hand, if SiF.sub.4 gas is used in the deposition, the previously deposited a-Si:H layer (active layer 13) is damaged by ions which are accelerated by SiF.sub.4 decomposed at a high RF power.